(a) Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, and more particularly to a method for forming a metal pattern in a semiconductor device.
(b) Description of the Related Art
As the degree of integration of semiconductor devices is increasing and performance of semiconductor devices is highly enhanced, reduction of contact resistivity when an interconnection contact is connected to a metal pattern, which is an interconnection provided above the interconnection contact, has become as a significant issue.
In fabricating a semiconductor device, a copper interconnection is used to reduce interconnection resistivity. A damascene process is used to form the copper interconnection. In addition, a tungsten (W) contact having relatively low resistivity is used as the interconnection contact in order to reduce the contact resistivity.
FIG. 1 is a schematic sectional view illustrating a method for forming a metal pattern in a related art semiconductor device.
Referring to FIG. 1, transistor elements are formed on a semiconductor substrate 10. A device isolation film 15 is formed, for example by shallow trench isolation (STI), on the semiconductor substrate 10. A gate oxide film 21 and a gate 23 are formed on a device region. A buffer layer 25 is formed on a sidewall of the gate 23, and a sidewall spacer 27 is formed on the buffer layer 25. Source/drain regions 31 are formed in the vicinity of gate 23 on the semiconductor substrate 10. A metal silicide layer 29 for resistivity reduction is formed on the gate 23. A metal silicide layer 35 is formed on the source/drain regions 31.
A first lower insulating layer 41 having a liner shape is formed covering the above transistor structure. A second lower insulating layer 43 and a third lower insulating layer 45 are sequentially stacked on the first lower insulating layer 41 to implement an insulating layer structure.
An interconnection contact 55 electrically connected to the source/drain region 31 through the insulating layer structure is formed within a contact hole 47. The interconnection contact 55 is made of tungsten. A barrier metal layer 51 is formed with a Ti/TiN layer under the tungsten interconnection contact 55. In this case, the Ti layer has a thickness of about 300Å and the TiN layer has a thickness of about 50Å.
A first upper insulating layer 61 and a second upper insulating layer 63 covering the interconnection contact 55 are formed. Also, a metal pattern 75 of a copper interconnection contacting with a top surface of the interconnection contact 55 through the first upper insulating layer 61 and the second upper insulating layer 63 is formed by performing a single damascene process. A Ta/TaN layer having a thickness of 150 Å/ 150Å is formed as a barrier metal layer 71 under the metal pattern 75 of the copper interconnection.
The tungsten interconnection contact 55 contacts the metal pattern 75 of the copper interconnection with an unacceptably high contact resistivity. This is because the resistivity of tungsten is about four times as large as that of copper, which results in deterioration in the performance of the semiconductor device.